Baud-rate clock recovery lock point control

ABSTRACT

A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating an example system.

FIGS. 2A-2C are block diagrams illustrating example systems.

FIGS. 3A-3D are diagrams illustrating example phase lock point adjustments using PAM-2 signaling.

FIGS. 4A-4B are diagrams illustrating example phase lock point adjustment using PAM-4 signaling.

FIG. 5 is a flowchart illustrating a method of phase locking.

FIG. 6 is a flowchart illustrating a method of calibrating a phase detector.

FIG. 7 is a block diagram illustrating a processing system.

DETAILED DESCRIPTION OF THE EMBODIMENTS

An integrated circuit may communicate with another integrated circuit using one or more high-speed serial data streams that are sent without an accompanying clock signal. The receiver of this data stream generates a local timing reference clock from an approximate frequency reference clock by phase-aligning the frequency reference clock (a.k.a., receiver reference clock, or receiver clock) to transitions in the data stream. This process is commonly known as clock and data recovery (CDR).

In an embodiment, certain transitions of the data signals are selected for use in phase-aligning the local clock, and certain transitions are ignored. The selected transitions are based on data patterns and the outputs of two error slicers/samplers. In particular, a transition will be indicated to phase-aligning circuitry as being early based on a first data pattern and the output of an early error sampler that is set to have a first threshold voltage. A transition will be indicated to phase-aligning circuitry as being late based on a second data pattern and the output of a late error sampler that is set to have a second threshold voltage that is not equal to the first threshold.

In an embodiment, by adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.

FIG. 1 is a block diagram illustrating an example system. In FIG. 1 , communication system 100 comprises a driving integrated circuit 110, a receiving integrated circuit 150, and interconnect 140 between them. Driving integrated circuit 110 includes transmitter circuit 111 (a.k.a., a driver), and transmit clock source 119. Receiving integrated circuit 150 includes one or more data sampler circuits 151 (a.k.a., data samplers or data slicers), early error sampler 152, late error sampler 153, control circuitry 130, phase adjustment circuit 170, and receiver clock source 190. Interconnect 140 typically comprises a printed circuit (PC) board, connector, cable, flex circuit, other substrate, and/or a combination of these. Interconnect 140 may be and/or include one or more transmission lines. It should also be understood that although system 100 is illustrated as transmitting a single-ended signal, the signals sent by the driving integrated circuit 110 of system 100 may represent a pair of differential signals.

Driving integrated circuit 110 comprises a transmitter circuit 111. Transmitter circuit 111 is operatively coupled to transmit clock source 119 to receive at least one timing reference signal that determines when data received by transmitter circuit 111 from driving integrated circuit 110 is output by transmitter circuit 111.

The output of transmitter circuit 111 is coupled to the data inputs of data samplers 151, the data input of early error sampler 152, and late error sampler 153 via interconnect 140. Data samplers 151 receive a sample clock (CK) from phase adjustment 170. Data samplers 151 sample (or resolve) the voltage level at their data input (i.e., from interconnect 140) against one or more threshold voltages (e.g., PAM-4 compatible threshold voltages of -α, 0, and +α for M=3) according to timing provided by sample clock CK. Early error sampler 152 and late error sampler 153 also receive the sample clock CK from phase adjustment 170. Early error sampler 152 samples (or resolves) the voltage level at its data input (i.e., from interconnect 140) against an early threshold voltage, V_(E), received from control circuitry 130 according to timing provided by sample clock CK. Late error sampler 153 samples (or resolves) the voltage level at its data input (i.e., from interconnect 140) against a late threshold voltage, V_(L), received from control circuitry 130 according to timing provided by sample clock CK.

The M outputs from data samplers 151 may be decoded to produce N number of received bits. For example, for PAM-4 communication system, three (3) data samplers (i.e., M=3) are used to compare the input voltage to three threshold voltages (-α, 0, and +α). These three outputs may be decoded to produce a two (2) bit output. This two bit output may be represented by the numbers 3,1,-1, and 3. In another example, for PAM-2 communication system, one (1) data sampler (i.e., M=1) can be used to compare the input voltage to a single threshold voltage (e.g., 0). This output corresponds to a one (1) bit output represented by the numbers 0 and 1.

In other words, for example, in response to one of the edges on CK (e.g., rising edge) a particular data sampler 151 determines whether the voltage at that sampler 151′s input is greater than, or less than, a particular threshold (e.g., 1.0 V, 0.0 V, or +α volts) The output of that sampler corresponds to whether the voltage at the input to that sampler is greater than, or less than, the threshold.

In FIG. 1 , there are M number of data samplers 151. Thus, the number of outputs from data samplers 151 is M signals respectively indicating whether the voltage at the inputs of these M data samplers 151 is greater than, or less than, the corresponding M number of threshold voltages. These M signals are provided to phase adjustment 170 and control circuitry 130.

Receiving integrated circuit 150 also includes receiver clock source 190. Receiver clock source 190 is operatively coupled to phase adjustment 170. Phase adjustment 170 receives a clock signal (RCK) from receiver clock source 190. Phase adjustment 170 changes the phase of clock signal RCK to produce phase-adjusted clock signal CK.

Phase adjustment 170 provides a phase-adjusted clock signal CK to data samplers 151, early error sampler 152, and late error sampler 153 of receiving integrated circuit 150. Based on a data pattern comprising the data symbols from three consecutive samples (d₋₁, d₀, d₊₁), and an error sample (e.g., e_(E0) from early error sampler 152 or e_(L0) from late error sampler 153) taken at the same time as the middle of the three sampled, phase adjustment 170 adjusts the phase change applied to the clock signal RCK to produce phase-adjusted clock signal CK.

In particular, for example, when the three consecutive samples taken by data samplers 151 are, for PAM-2 signaling, d₋₁=0, d₀=1, and d₊₁=1, and the early error sampler 152 sampled e_(E0)=0 coincident with the d₀ sample, it indicates to phase adjustment 170 that phase-adjusted clock signal CK is too early relative to the data stream (DS) being received. In response, phase adjustment 170 adjusts phase-adjusted clock signal CK to increase the phase difference between the data stream being received and phase-adjusted clock CK. When the three consecutive samples taken by data samplers 151 are, for PAM-2 signaling, d₋₁=1, d₀=1, and d₊₁=0, and the late error sampler 153 sampled e_(L0)=0 coincident with the d₀ sample, it indicates to phase adjustment 170 that phase-adjusted clock signal CK is too late relative to the data stream (DS) being received. In response, phase adjustment 170 adjusts phase-adjusted clock signal CK to decrease the phase difference between the data stream being received and phase-adjusted clock CK. In an embodiment, the data and error sample patterns {d₋₁=0, d₀=1, d₊₁=1, e_(E0)=0} and {d-₁=1, d₀=1, d₊₁=0, e_(L0)=0} are the only patterns that cause phase adjustment 170 to adjust the phase of phase-adjusted clock signal CK. It should be understood that these data patterns are examples. Other data patterns may be used as indicators that the phase of the phase-adjusted clock signal should be adjusted.

In another example, for PAM-4 signaling, when the three consecutive samples taken by data samplers 151 are d₋₁=-3 or -1, d₀=3, and d₊₁=3, and the early error sampler 152 sampled e_(E0)=0 coincident with the d₀ sample, it indicates to phase adjustment 170 that phase-adjusted clock signal CK is too early relative to the data stream (DS) being received. In response, phase adjustment 170 adjusts phase-adjusted clock signal CK to increase the phase difference between the data stream being received and phase-adjusted clock CK. When the three consecutive samples taken by data samplers 151 are d₋₁=3, d₀=3, and d₊₁=-1 or -3, and the late error sampler 153 sampled e_(L0)=0 coincident with the d₀ sample, it indicates to phase adjustment 170 that phase-adjusted clock signal CK is too late relative to the data stream (DS) being received. In response, phase adjustment 170 adjusts phase-adjusted clock signal CK to decrease the phase difference between the data stream being received and phase-adjusted clock CK. In an embodiment, the data and error sample patterns {d₋₁=-3, d₀=3, d₊₁=3, e_(E0)=0}, {d₋₁=-1, d₀=3, d₊₁=3, e_(E0)=0}, {d₋₁=3, d₀=3, d₊₁=-1, e_(L0)=0} and {d₋₁=3, d₀=3, d₊₁=-3, e_(L0)=0} are the only patterns that cause phase adjustment 170 to adjust the phase of phase-adjusted clock signal CK. It should be understood that these data patterns are examples. Other data patterns may be used as indicators that the phase of the phase-adjusted clock signal should be adjusted.

In an embodiment, control circuitry 130 uses early threshold voltage V_(E) and late threshold voltage V_(L) to adjust/change/control the phase of phase-adjusted clock signal CK relative to the transitions of the data (DS) being received from driving integrated circuit 110. For example, control circuitry 130 may set the difference (ΔV_(T)) between early threshold voltage V_(E) and late threshold voltage V_(L) to optimize a particular figure-of-merit such as bit error rate (BER) or signal eye opening. Example pseudo-code for optimization/calibration is given in Table 1.

TABLE 1 Loop ΔV_(T) from 1:1 V_(T)-min to ΔV_(T)-max in steps of ΔV_(T)-step Determine figure-of-merit (FOM) at current ΔV_(T) If current FOM is better than any previous FOM, then: Save current ΔV_(T) value as best setting End loop Set ΔV_(T) to best ΔV_(T) value.

FIGS. 2A-2C are a block diagrams illustrating an example system. In FIG. 2A, communication system 200 comprises a driving integrated circuit 210, a receiving integrated circuit 250, and interconnect 240 between them. Driving integrated circuit 210 includes transmitter circuit 211 (a.k.a., a driver), control circuitry 215, and pattern circuitry 218, and transmit clock source 219. Receiving integrated circuit 250 includes one or more data sampler circuits 251 (a.k.a., data samplers or data slicers), error sampler 252, control circuitry 230, phase adjustment circuit 270, and receiver clock source 290. Control circuitry 230 includes digital-to-analog converter (DAC) 231 and registers 232. Interconnect 240 typically comprises a printed circuit (PC) board, connector, cable, flex circuit, other substrate, and/or a combination of these. Interconnect 240 may be and/or include one or more transmission lines. It should also be understood that although system 200 is illustrated as transmitting a single-ended signal, the signals sent by the driving integrated circuit 210 of system 200 may represent a pair of differential signals.

Driving integrated circuit 210 comprises a transmitter circuit 211. Transmitter circuit 211 is operatively coupled to transmit clock source 219 to receive at least one timing reference signal that determines when data received by transmitter circuit 211 from driving integrated circuit 210 is output by transmitter circuit 211. Driving integrated circuit 210 includes control circuitry 215 and pattern circuitry 218. Pattern circuitry 218 may be configured by control circuitry 215 to provide a repeating pattern to be transmitted by transmitter circuit 211 to receiving integrated circuit 250. The repeating pattern may be a calibration pattern.

The output of transmitter circuit 211 is coupled to the data inputs of data samplers 251 and error sampler 252 via interconnect 240. Data samplers 251 receive a sample clock (CK) from phase adjustment 270. Data samplers 251 sample (or resolve) the voltage level at their data input (i.e., from interconnect 240) against one or more threshold voltages (e.g., PAM-4 compatible threshold voltages of -α, 0, and +α for M=3) according to timing provided by sample clock CK. Error sampler 252 also receives the sample clock CK from phase adjustment 270. Error sampler 252 samples (or resolves) the voltage level at its data input (i.e., from interconnect 240) against a controllable threshold voltage, V_(T), received from control circuitry 230 according to timing provided by sample clock CK.

DAC 231 is controlled by register 232 to output an analog voltage level (V_(T)) that is used as a threshold voltage for error sampler 252. Control circuitry 230 provides a signal (E/L) to phase adjustment 270 indicating whether the threshold voltage being provided to error sampler 252 corresponds to an early threshold voltage (V_(E)) or a late threshold voltage (V_(L)). In this manner, a single error sampler may be used as both an early error sample and a late error sampler.

The M outputs from data samplers 251 may be decoded to produce N number of received bits. For example, for PAM-4 communication system, three (3) data samplers (i.e., M=3) are used to compare the input voltage to three threshold voltages (-α, 0, and +α). These three outputs may be decoded to produce a two (2) bit output. This two bit output may be represented by the numbers 3,1,-1, and 3. In another example, for PAM-2 communication system, one (1) data sampler (i.e., M=1) can be used to compare the input voltage to a single threshold voltage (e.g., 0). This output corresponds to a one (1) bit output represented by the numbers 0 and 1.

In FIGS. 2A-2C, there are M number of data samplers 251. Thus, the number of outputs from data samplers 251 is M signals respectively indicating whether the voltage at the inputs of these M data samplers 251 is greater than, or less than, the corresponding M number of threshold voltages. These M signals are provided to phase adjustment 270 and control circuitry 230.

Receiving integrated circuit 250 also includes receiver clock source 290. Receiver clock source 290 is operatively coupled to phase adjustment 270. Phase adjustment 270 receives a clock signal (RCK) from receiver clock source 290. Phase adjustment 270 changes the phase of clock signal RCK to produce phase-adjusted clock signal CK.

Phase adjustment 270 provides a phase-adjusted clock signal CK to data samplers 251, and error sampler 252 of receiving integrated circuit 250. Based on a data pattern comprising the data symbols from three consecutive samples (d₋₁, d₀, d₊₁), and an error sample (e.g., e₀ from error sampler 252) taken at the same time as the middle of the three samples, phase adjustment 270 adjusts the phase change applied to the clock signal RCK to produce phase-adjusted clock signal CK.

In particular, for example, when the three consecutive samples taken by data samplers 251 are, for PAM-2 signaling, d₋₁=0, d₀=1, and d₊₁=1, register 232 is controlling DAC 231 to output an early threshold voltage level (i.e., V_(T)=V_(E) and E/L signal indicates “early”), and the error sampler 252 sampled e₀=0 coincident with the d₀ sample, it indicates to phase adjustment 270 that phase-adjusted clock signal CK is too early relative to the data stream (DS) being received. In response, phase adjustment 270 adjusts phase-adjusted clock signal CK to increase the phase difference between the data stream being received and phase-adjusted clock CK. When the three consecutive samples taken by data samplers 251 are, for PAM-2 signaling, d₋₁=1, d₀=1, and d₊₁=0, register 232 is controlling DAC 231 to output a late threshold voltage level (i.e., V_(T)=V_(L) and E/L signal indicates “late”), and the error sampler sampled e₀=0 coincident with the d₀ sample, it indicates to phase adjustment 270 that phase-adjusted clock signal CK is too late relative to the data stream (DS) being received. In response, phase adjustment 270 adjusts phase-adjusted clock signal CK to decrease the phase difference between the data stream being received and phase-adjusted clock CK. In an embodiment, the data and error sample patterns {d₋₁=0, d₀=1, d₊₁=1, e₀=0 when V_(T)=V_(E)} and {d₋₁=1, d₀=1, d₊₁=0, e₀=0 when V_(T)=V_(L) } are the only patterns that cause phase adjustment 270 to adjust the phase of phase-adjusted clock signal CK. It should be understood that these data patterns are examples. Other data patterns may be used as indicators that the phase of the phase-adjusted clock signal should be adjusted.

In another example, for PAM-4 signaling, when the three consecutive samples taken by data samplers 251 are d₋₁=-3 or -1, d₀=3, and d₊₁=3, register 232 is controlling DAC 231 to output an early threshold voltage level (i.e., V_(T)=V_(E) and E/L signal indicates “early”), and error sampler 252 sampled e₀=0 coincident with the d₀ sample, it indicates to phase adjustment 270 that phase-adjusted clock signal CK is too early relative to the data stream (DS) being received. In response, phase adjustment 270 adjusts phase-adjusted clock signal CK to increase the phase difference between the data stream being received and phase-adjusted clock CK. When the three consecutive samples taken by data samplers 251 are d₋₁=3, d₀=3, and d₊₁=-1 or -3, register 232 is controlling DAC 231 to output a late threshold voltage level (i.e., V_(T)=V_(L) and E/L signal indicates “late”), and the error sampler sampled e₀=0 coincident with the d₀ sample, it indicates to phase adjustment 270 that phase-adjusted clock signal CK is too late relative to the data stream (DS) being received. In response, phase adjustment 270 adjusts phase-adjusted clock signal CK to decrease the phase difference between the data stream being received and phase-adjusted clock CK. In an embodiment, the data and error sample patterns {d₋₁=-3, d₀=3, d₊₁=3, e₀=0 when V_(T)=V_(E) }, {d₋₁=-1, d₀=3, d₊₁=3, e₀=0 when V_(T)=V_(E) }, {d₋₁=3, d₀=3, d+₁=-1, e₀=0 when V_(T)=V_(L) } and {d₋₁=3, d₀=3, d₊₁=-3, e₀=0 when V_(T)=V_(L) } are the only patterns that cause phase adjustment 270 to adjust the phase of phase-adjusted clock signal CK. It should be understood that these data patterns are examples. Other data patterns may be used as indicators that the phase of the phase-adjusted clock signal should be adjusted.

In an embodiment, control circuitry 230 uses early threshold voltage V_(E) and late threshold voltage V_(L) to adjust/change/control the phase of phase-adjusted clock signal CK relative to the transitions of the data (DS) being received from driving integrated circuit 210. For example, control circuitry 230 may set the difference (ΔV_(T)) between early threshold voltage V_(E) and late threshold voltage V_(L) to optimize a particular figure-of-merit such as bit error rate (BER) or signal eye opening.

FIG. 2B is a block diagram illustrating an example system. In FIG. 2B, communication system 201 comprises a driving integrated circuit 210, a receiving integrated circuit 250, and interconnect 240 between them. Driving integrated circuit 210 includes transmitter circuit 211 (a.k.a., a driver), control circuitry 215, and pattern circuitry 218, and transmit clock source 219. Receiving integrated circuit 250 includes one or more data sampler circuits 251 (a.k.a., data samplers or data slicers), error sampler 252, control circuitry 230, phase adjustment circuit 270, and receiver clock source 290. Control circuitry 230 includes digital-to-analog converter (DAC) 231 and registers 232.

System 201 functions similarly to system 200 of FIG. 2A except that control circuitry 215 of driving integrated circuit 210 sets the threshold voltages used by error sampler 252. Thus, system 201 also includes link 235 and link 236. Link 235 is between control circuitry 215 and control circuitry 230 so that control circuitry 230 may set the value in register 232 thereby setting the threshold voltage V_(T). Link 236 provides outputs of data samplers 251 to control circuitry 215.

Control circuitry 215 uses early threshold voltage V_(E) and late threshold voltage V_(L) to adjust/change/control the phase of phase-adjusted clock signal CK relative to the transitions of the data (DS) being transmitted from driving integrated circuit 210. For example, control circuitry 215 may set the difference (ΔV_(T)) between early threshold voltage V_(E) and late threshold voltage V_(L) to optimize a particular figure-of-merit as indicated by such as bit error rate (BER) or signal eye opening. Control circuitry 215 may set the difference (ΔV_(T)) between early threshold voltage V_(E) and late threshold voltage V_(L) to optimize a particular figure-of-merit that is based on the outputs of data samplers 251.

FIG. 2C is a block diagram illustrating an example system. In FIG. 2C, communication system 202 comprises a driving integrated circuit 210, a receiving integrated circuit 250, and interconnect 240 between them. Driving integrated circuit 210 includes transmitter circuit 211 (a.k.a., a driver), control circuitry 215, and pattern circuitry 218, and transmit clock source 219. Receiving integrated circuit 250 includes one or more data sampler circuits 251 (a.k.a., data samplers or data slicers), error sampler 252, control circuitry 230, phase adjustment circuit 270, and receiver clock source 290. Control circuitry 230 includes digital-to-analog converter (DAC) 231 and registers 232.

System 202 functions similarly to system 200 of FIG. 2A except that control circuitry 230 of receiving integrated circuit 230 can set the pattern generated by pattern generation circuitry 218 thereby setting the pattern transmitted to receiving integrated circuit. Thus, system 202 also includes link 237. Link 237 is between control circuitry 230 and control circuitry 215 so that control circuitry 230 may set the pattern generated by pattern generation circuitry 218.

Thus, for example, control circuitry 230 may set a first pattern to adjust the early threshold voltage V_(E) and second pattern to adjust the late threshold voltage V_(L). Control circuitry 230 may to adjust/change/control the phase of phase-adjusted clock signal CK relative to the transitions of the data (DS) being transmitted from driving integrated circuit 210. For example, control circuitry 215 may set the difference (ΔV_(T)) between early threshold voltage V_(E) and late threshold voltage V_(L) to optimize a particular figure-of-merit as indicated by such as bit error rate (BER) or signal eye opening.

FIGS. 3A-3D are diagrams illustrating example phase lock point adjustments using PAM-2 signaling. In FIGS. 3A-3D, time is increasing from left to right. In FIGS. 3A-3D waveform 301 illustrates an example PAM-2 rising edge for the pattern {d₋₁=0, d₀=1, d₊₁=1}. Waveform 302 illustrates an example PAM-2 falling edge for the pattern {d₋₁=1, d₀=1, d₊₁=0}. In FIG. 3A, early threshold voltage V_(E) and late threshold voltage V_(L) are controlled by control circuitry 130 to be equal (i.e., ΔV_(T)=0). Sampling times (i.e., phase differences) to the left (i.e., earlier in time) of sampling time 375 indicate to phase adjustment 170 that the phase difference between the incoming data signal and phase-adjusted clock CK is too small (i.e., early) because to the left of sampling time 375 waveform 301 is less than V_(E). Sampling times to the right (i.e., later in time) of sampling time 375 indicate to phase adjustment 170 that the phase difference between the incoming data signal and phase-adjusted clock CK is not too small (i.e., early) because to the right of sampling time 375 waveform 301 is greater than V_(E). Sampling times (i.e., phase differences) to the right (i.e., later in time) of sampling time 376 indicate to phase adjustment 170 that the phase difference between the incoming data signal and phase-adjusted clock CK is too large (i.e., late) because to the right of sampling time 376 waveform 302 is less than V_(L). Sampling times to the left (i.e., earlier in time) of sampling time 376 indicate to phase adjustment 170 that the phase difference between the incoming data signal and phase-adjusted clock CK is not too large (i.e., late) because to the left of sampling time 376 waveform 302 is greater than V_(L). The midpoint between sampling times 375 and 376 is illustrated in FIG. 3A by arrow 331. Arrow 331 corresponds to the lock point of the baud-rate phase detector.

In FIG. 3B, early threshold voltage V_(E) and late threshold voltage V_(L) are controlled by control circuitry 130 to be unequal (i.e., ΔV_(T)≠0). In particular, in FIG. 3B, V_(E)<V_(L) where the V_(L) illustrated in FIG. 3B is the same as the V_(L) in FIG. 3A. Similar to FIG. 3A but with a different V_(E), sampling times (i.e., phase differences) to the left (i.e., earlier in time) of sampling time 377 indicate to phase adjustment 170 that the phase difference between the incoming data signal and phase-adjusted clock CK is too small (i.e., early) because to the left of sampling time 377 waveform 301 is less than V_(E). Sampling times to the right (i.e., later in time) of sampling time 377 indicate to phase adjustment 170 that the phase difference between the incoming data signal and phase-adjusted clock CK is not too small (i.e., early) because to the right of sampling time 375 waveform 301 is greater than V_(E).

Note that by lowering V_(E) relative to its level in FIG. 3A has moved sampling time 377 left (earlier in time) relative to sampling time 375 in FIG. 3A. The midpoint between sampling times 377 and 376 is illustrated in FIG. 3B by arrow 332. Note that by moving sampling time 377 earlier in time, the midpoint between sampling time 377 and sampling time 376 (as illustrated by midpoint arrow 332) is earlier than the midpoint between sampling time 375 and sampling time 376 (as illustrated by midpoint arrow 331.) Thus, by adjusting the difference between V_(E) and V_(L), (and/or the values of V_(E) and V_(L)) the midpoint of the range where adjustment is called for by the data/error patterns is also adjusted. This allows control circuitry 130 to control the timing of the midpoint in order to optimize a figure-of-merit.

FIG. 3C illustrates the effect of that different early threshold voltages has on the early error indication of the d₀ sampling time. In FIG. 3C, the sampling time limits where phase adjustment 170 will take action to correct a sampling time that is too early is illustrated for two different early threshold voltages V_(E1) and V_(E2), where V_(E1)>V_(E2). As is illustrated in FIG. 3C, this results in two different sampling times 377 and 375 that divide sampling times that result in error indicators that phase adjustment 170 should take action to correct the phase of CK from those sampling times that result in error indicators that phase adjustment 170 should not take action to correct the phase of CK. These sampling times 377 and 375 are separated by an amount of time Δ_(E). Thus, adjusting V_(E) can be used to control the location of the sampling time that causes phase adjustment 170 to correct for an early sampling time vs. not taking any action regarding the rising edge pattern {d₋₁=0, d₀=1, d₊₁=1}.

FIG. 3D illustrates the effect of that different late threshold voltages has on the late error indication of the d₀ sampling time. In FIG. 3D, the sampling time limits where phase adjustment 170 will take action to correct a sampling time that is too late is illustrated for two different late threshold voltages V_(L1) and V_(L2), where V_(L1)>V_(L2). As is illustrated in FIG. 3D, this results in two different sampling times 376 and 378 that divide sampling times that resulting in error indicators that phase adjustment 170 should take action to correct the phase of CK from those sampling times that result in error indicators that phase adjustment 170 should not take action to correct the phase of CK. These sampling times 376 and 378 are separated by an amount of time Δ_(L). Thus, adjusting V_(L) can be used to control the location of the sampling time that causes phase adjustment 170 to correct for a late sampling time vs. not taking any action regarding the falling edge pattern {d₋₁=1, d₀=1, d₊₁=0}.

FIGS. 4A-4B are diagrams illustrating example phase lock point adjustments with PAM-4 signaling. In FIGS. 4A-4B, time is increasing from left to right. In FIG. 4A, waveform 401 illustrates an example PAM-4 rising edge for the pattern {d₋₁=-1, d₀=3, d₊₁=3}. Waveform 402 illustrates an example PAM-4 rising edge for the pattern {d₋₁=-3, d₀=3, d₊₁=3}. In FIG. 4A, d₀ sample timing is illustrated for two different early threshold voltages V_(E1) and V_(E2), where V_(E1)>V_(E2). As is illustrated in FIG. 4A, this results in two different sampling times that divide sampling times that result in error indicators that phase adjustment 170 should take action to correct the phase of CK from those sampling times that result in error indicators that phase adjustment 170 should not take action to correct the phase of CK. These sampling times are separated by an amount of time Δ_(E) Thus, adjusting V_(E) for a PAM-4 input signal can be used to control the location of the sampling time that causes phase adjustment 170 to correct for an early sampling time vs. not taking any action regarding the rising edge patterns {d₋₁=-1, d₀=3, d₊₁=3} and {d₋₁=-3, d₀=3, d₊₁=3}.

In FIG. 4B, waveform 403 illustrates an example PAM-4 falling edge for the pattern {d₋₁=3, d₀=3, d₊₁=-3}. Waveform 404 illustrates an example PAM-4 falling edge for the pattern {d₋₁=3, d₀=3, d₊₁=-1}. In FIG. 4B, d₀ sample timing is illustrated for two different late threshold voltages V_(L1) and V_(L2), where V_(L1)>V_(L2). As is illustrated in FIG. 4B, this results in two different sampling times that divide sampling times that result in error indicators that phase adjustment 170 should take action to correct the phase of CK from those sampling times that result in error indicators that phase adjustment 170 should not take action to correct the phase of CK. These sampling times are separated by an amount of time Δ_(L) Thus, adjusting V_(L) for a PAM-4 input signal can be used to control the location of the sampling time that causes phase adjustment 170 to correct for a late sampling time vs. not taking any action regarding the falling edge patterns {d₋₁=3, d₀=3, d₊₁=-3} and {d₋₁=3, d₀=3, d₊₁=-1}.

FIG. 5 is a flowchart illustrating a method of phase locking. One or more steps illustrated in FIG. 5 may be performed by, for example, system 100, system 200, system 201, system 202, and/or their components. A first early error sample value is generated by comparing, at a first sampling time, a data signal to a first error threshold voltage (502). For example, during a first cycle of CK and at a first sampling time determined by the phase of CK relative to input data signal DS, early error sampler 152 may produce, by comparing the input signal DS to a first threshold voltage value V_(E1), a first early error sample value that is supplied to phase adjustment 170. A first data sample value is generated by comparing, at the first sampling time, the data signal to at least a first data threshold voltage (504). For example, during the first cycle of CK and at the first sampling time as determined by the phase of CK relative to input data signal DS, data samplers 151 may produce, by comparing the input data signal to an appropriate threshold voltage(s), a one (for PAM-2) or more (for PAM-4 etc.) data sample values that are supplied to phase adjustment 170.

Based on the first early error sample value and the first data sample value, a first early error signal value is generated (506). For example, based on e_(E0) being equal to 0, and d₀ being equal to 1 as part of the rising edge pattern {d₋₁=0, d₀=1, d₊₁=1}, phase adjustment 170 may internally determine an early error signal value that indicates whether or not to adjust the phase difference between CK relative to the input signal DS because CK is occurring too early (or not) relative to the input data signal DS.

A first late error sample value is generated by comparing, at a second sampling time, the data signal to a second error threshold voltage (508). For example, during a second (different from the first) cycle of CK and thereby being at a second sampling time that is also determined by the phase of CK relative to input data signal DS, late error sampler 153 may produce, by comparing the input signal DS to a second threshold voltage value V_(L1), a first late error sample value that is supplied to phase adjustment 170. A second data sample value is generated by comparing, at the second sampling time, the data signal to at least the first data threshold voltage (510). For example, during the second cycle of CK and at the second sampling time as determined by the phase of CK relative to input data signal DS, data samplers 151 may produce, by comparing the input data signal to an appropriate threshold voltage(s), a one (for PAM-2) or more (for PAM-4 etc.) data sample values that are supplied to phase adjustment 170.

Based on the first late error sample value and the second data sample value, a first late error signal value is generated (512). For example, based on e_(L0) being equal to 0, and d₀ being equal to 1 as part of the falling edge pattern {d₋₁=1, d₀=1, d₊₁=0}, phase adjustment 170 may internally determine a late error signal value that indicates whether or not to adjust the phase difference between CK relative to the input signal DS because CK is occurring too late (or not) relative to the input data signal DS.

Based on the first early error signal value and the first late error signal value, a phase relationship between the data signal and a timing reference that determined the first sampling time and the second sampling time is adjusted (514). For example, based on the early error signal value and the late error signal value, phase adjustment 170 may adjust the phase of CK relative to the input data signal DS. In other words, if the early error signal value indicated that CK was too early relative to DS, phase adjustment 170 may increase the phase delay from the transitions on DS and the transitions on CK that cause samplers 151-153 to sample. Likewise, if the late error signal value indicated that CK was too late relative to DS, phase adjustment 170 may decrease the phase delay from the transitions on DS and the transitions on CK that cause samplers 151-153 to sample. If neither the early error signal value nor the late error signal value indicated an adjustment was indicated, phase adjustment 170 may, for example, not make an adjustment.

FIG. 6 is a flowchart illustrating a method of calibrating a phase detector. One or more steps illustrated in FIG. 6 may be performed by, for example, system 100, system 200, system 201, system 202, and/or their components. A plurality of early threshold voltages are selected (602). For example, control circuitry 130 select range (e.g., V_(E,min) to V_(E,max)) and voltage step (e.g., V_(E,step)) for V_(E).

A one of the plurality of early threshold voltages are each successively provided to an early error sampler of a baud-rate phase detector to be used as an early error sampler threshold voltage (604). For example, control circuitry 130 may successively supply early error sampler 152 with early error threshold voltages V_(E) that are swept through the selected range V_(E,min) to V_(E,max) at the selected step V_(E),_(step).

A plurality of late threshold voltages are selected (606). For example, control circuitry 130 select range (e.g., V_(L,min) to V_(L,max)) and voltage step (e.g., V_(L,step)) for V_(L). A one of the plurality of late threshold voltages are each successively provided to a late error sampler of the baud-rate phase detector to be used as a late error sampler threshold voltage (608). For example, control circuitry 130 may successively supply late error sampler 153 with late error threshold voltages V_(L) that are swept through the selected range V_(L),_(min) to V_(L),_(max) at the selected step V_(L),_(step).

While operating the baud-rate phase detector with respective ones of the plurality of early threshold voltages and respective ones of the plurality of late threshold voltages, a plurality of performance indicators are determined that correspond to an association between the respective ones of the plurality of early threshold voltages and respective ones of the plurality of late threshold voltages while the baud-rate phase detector is controlling the phase difference between a data signal and a timing reference (610). For example, while receiving integrated circuit 150 is receiving a data stream DS from driving integrated circuit 110 via interconnect 140, control circuitry 130 may sweep one or more of V_(E) and V_(L). At each step in the sweep(s), control circuitry 130 may wait for the feedback loop formed by samplers 151-153 and phase adjustment 170 to settle. Once the feedback loop has settled, control circuitry may determine a performance indicator (a.k.a., figure-of-merit) for the current settings.

Based on the plurality of performance indicators, a one of the plurality of early threshold voltages and a one of the plurality of late threshold voltages are selected (612). For example, based on the performance indicators associated with each of the V_(E) and/or V_(L) settings that were tried, control circuitry 130 may select values for V_(E) and/or V_(L) that optimizes (e.g., minimizes or maximizes, as appropriate) the performance indicator (e.g., BER, eye characteristic.)

The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of system 100, and its components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-½ inch floppy media, CDs, DVDs, and so on.

FIG. 7 is a block diagram illustrating one embodiment of a processing system 700 for including, processing, or generating, a representation of a circuit component 720. Processing system 700 includes one or more processors 702, a memory 704, and one or more communications devices 706. Processors 702, memory 704, and communications devices 706 communicate using one or more serial links 708 a-708 b. Serial links 708 a-708 b may communicate and/or be calibrated using the circuits and techniques described herein.

Processors 702 execute instructions of one or more processes 712 stored in a memory 704 to process and/or generate circuit component 720 responsive to user inputs 714 and parameters 716. Processes 712 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and/or verify electronic circuitry and/or generate photomasks for electronic circuitry. Representation 720 includes data that describes all or portions of system 100, and its components, as shown in the Figures.

Representation 720 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 720 may be stored on storage media or communicated by carrier waves.

Data formats in which representation 720 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email

User inputs 714 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 716 may include specifications and/or characteristics that are input to help define representation 720. For example, parameters 716 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and/or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

Memory 704 includes any suitable type, number, and/or configuration of non-transitory computer-readable storage media that stores processes 712, user inputs 714, parameters 716, and circuit component 720.

Communications devices 706 include any suitable type, number, and/or configuration of wired and/or wireless devices that transmit information from processing system 700 to another processing or storage system (not shown) and/or receive information from another processing or storage system (not shown). For example, communications devices 706 may transmit circuit component 720 to another system. Communications devices 706 may receive processes 712, user inputs 714, parameters 716, and/or circuit component 720 and cause processes 712, user inputs 714, parameters 716, and/or circuit component 720 to be stored in memory 704.

Implementations discussed herein include, but are not limited to, the following examples:

Example 1: An integrated circuit, comprising: a sampling timing reference to be phase adjusted relative to a data signal based on an early error signal and a late error signal; and a baud-rate phase detector to provide the early error signal and the late error signal, the early error signal to be based on an early error sample that used a first error threshold voltage, the late error signal to be based on a late error sample, the first error threshold voltage not equal to the second error threshold voltage.

Example 2: The integrated circuit of example 1, wherein a first timing of the early error sample and a first data sample are determined by a same first transition of the sampling timing reference.

Example 3: The integrated circuit of example 2, wherein a second timing of the late error sample and a second data sample are determined by a same second transition of the sampling timing reference.

Example 4: The integrated circuit of example 1, wherein a first data sample and a second data sample further use at least a first data threshold voltage and a second data threshold voltage.

Example 5: The integrated circuit of example 4, wherein the data signal uses PAM-4 signaling.

Example 6: The integrated circuit of example 1, wherein the sampling timing reference comprises a plurality of timing references having different phases with respect to each other of the plurality of timing references.

Example 7: The integrated circuit of example 6, wherein the early error sample is taken by a first one of N number of early error samplers using a first error threshold voltage and the late error sample is taken by a first one of N number of late error samplers using a second error threshold voltage.

Example 8: A method of providing baud-rate phase detection, comprising: generating a first early error sample value by comparing, at a first sampling time, a data signal to a first error threshold voltage; generating a first data sample value by comparing, at the first sampling time, the data signal to at least a first data threshold voltage; based on the first early error sample value and the first data sample value, generating a first early error signal value; generating a first late error sample value by comparing, at a second sampling time, the data signal to a second error threshold voltage, the second error threshold voltage not equal to the first error threshold voltage; generating a second data sample value by comparing, at the second sampling time, the data signal to at least the first data threshold voltage; based on the first late error sample value and the second data sample value, generating a first late error signal value; and, based on the first early error signal value and the first late error signal value, adjust a phase relationship between the data signal and a timing reference that determined the first sampling time and the second sampling time.

Example 9: The method of example 8, wherein the first sampling time and the second sampling time are different in time by an integer multiple of a symbol period of the data signal, the integer multiple being greater than or equal to zero.

Example 10: The method of example 8, wherein the first data sample value is generated by further comparing, at the first sampling time, the data signal to at least a second data threshold voltage, and wherein the second data sample value is generated by further comparing, at the second sampling time, the data signal to at least the second data threshold voltage.

Example 11: The method of example 8, wherein the first early error signal value is further based on a third data sample value and a fourth data sample value, and the first late error signal value is further based on a fifth data sample value and a sixth data sample value.

Example 12: The method of example 11, further comprising: generating the third data sample value by comparing, at a third sampling time, the data signal to at least the first data threshold voltage, the third sampling time being a symbol period of the data signal before the first sampling time; generating the fourth data sample value by comparing, at a fourth sampling time, the data signal to at least the first data threshold voltage, the fourth sampling time being the symbol period of the data signal after the first sampling time; generating the fifth data sample value by comparing, at a fifth sampling time, the data signal to at least the first data threshold voltage, the fifth sampling time being the symbol period of the data signal before the second sampling time; and, generating the sixth data sample value by comparing, at a sixth sampling time, the data signal to at least the first data threshold voltage, the sixth sampling time being the symbol period of the data signal after the second sampling time.

Example 13: The method of example 8, further comprising: based on the first early error signal value and the first late error signal value, adjusting, to a first phase difference value, a phase difference between the data signal and a timing reference that determined the first sampling time and the second sampling time.

Example 14: The method of example 13, further comprising: while the phase difference between the data signal and the timing reference is operating at the first phase difference value, determining a first performance indicator.

Example 15: The method of example 14, further comprising: based on a second early error signal value and a second late error signal value, adjusting, to a second phase difference value, the phase difference between the data signal and the timing reference; while the phase difference between the data signal and the timing reference is operating at the second phase difference value, determining a second performance indicator; and, based on the first performance indicator and the second performance indicator, adjust at least one of the first error threshold voltage and the second error threshold voltage.

Example 16: The method of example 15, wherein the first performance indicator and the second performance indicator are based at least on a bit error rate of a received version of the data signal.

Example 17: The method of example 15, wherein the first performance indicator and the second performance indicator are based at least on a measurement of a vertical eye opening of a received version of the data signal.

Example 18: A method of adjusting a phase difference between a data signal and a timing reference, comprising: selecting a plurality of early threshold voltages; successively providing a one of the plurality of early threshold voltages to an early error sampler of a baud-rate phase detector to be used as an early error sampler threshold voltage; selecting a plurality late threshold voltages; successively providing a one of a plurality of late threshold voltages to a late error sampler of the baud-rate phase detector to be used as a late error sampler threshold voltage; while operating the baud-rate phase detector with respective ones of the plurality of early threshold voltages and respective ones of the plurality of late threshold voltages, determine a plurality of performance indicators that correspond to an association between the respective ones of the plurality of early threshold voltages and the respective ones of the plurality of late threshold voltages while the baud-rate phase detector is controlling the phase difference between the data signal and the timing reference; and, based on the plurality of performance indicators, select a selected one of the plurality of early threshold voltages and select a selected one of the plurality of late threshold voltages.

Example 19: The method of example 18, further comprising: provide the baud-rate phase detector with the selected one of the plurality of early threshold voltages and the selected one of the plurality of early threshold voltages.

Example 20: The method of example 19, wherein the data signal is a PAM-4 type signal.

The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art. 

1. (canceled)
 2. An integrated circuit, comprising: a plurality of samplers to produce at least a first early error sample value by comparing, at a first sampling time, a data signal to a first error threshold voltage, to produce at least a first data sample value by comparing, at the first sampling time, the data signal to at least a first data threshold voltage, to produce at least a first late error sample value by comparing, at a second sampling time, the data signal to a second error threshold voltage, and to produce at least a second data sample value by comparing, at the second sampling time, the data signal to at least the first data threshold voltage; circuitry to generate a first early error sample value based on the first early error sample value and the first data sample value, and to generate a first late error sample value based on the first late error sample value and the second data sample value; and phase adjustment circuitry to, based on the first early error sample value and the first late error sample value, adjust a phase relationship between the data signal and a timing reference signal that determined the first sampling time and the second sampling time.
 3. The integrated circuit of claim 2, wherein the first sampling time and the second sampling time are different in time by an integer multiple of a symbol period of the data signal, the integer multiple being greater than or equal to zero.
 4. The integrated circuit of claim 2, wherein the first data sample value is produced by also comparing, at the first sampling time, the data signal to at least a second data threshold voltage, and wherein the second data sample value is produced by also comparing, at the second sampling time, the data signal to at least the second data threshold voltage.
 5. The integrated circuit of claim 2, wherein the first early error sample value is further based on a third data sample value and a fourth data sample value, and the first late error sample value is further based on a fifth data sample value and a sixth data sample value.
 6. The integrated circuit of claim 5, wherein the plurality of samplers are to: produce the third data sample value by comparing, at a third sampling time, the data signal to at least the first data threshold voltage, the third sampling time to be a symbol period of the data signal immediately before the first sampling time; produce the fourth data sample value by comparing, at a fourth sampling time, the data signal to at least the first data threshold voltage, the fourth sampling time to be a symbol period of the data signal immediately after the first sampling time; produce the fifth data sample value by comparing, at a fifth sampling time, the data signal to at least the first data threshold voltage, the fifth sampling time to be a symbol period of the data signal immediately before the second sampling time; and produce the sixth data sample value by comparing, at a sixth sampling time, the data signal to at least the first data threshold voltage, the sixth sampling time to be a symbol period of the data signal immediately after the second sampling time.
 7. The integrated circuit of claim 2, wherein, based on the first early error sample value and the first late error sample value, the phase adjustment circuitry is to adjust a phase difference between the data signal and a timing reference signal that determined the first sampling time and the second sampling time to a first phase difference value.
 8. The integrated circuit of claim 7, further comprising: control circuitry to, while the phase difference between the data signal and the timing reference is operating at the first phase difference value, determine a performance indicator.
 9. The integrated circuit of claim 8, wherein the performance indicator is to be based on at least a bit error rate of a received version of the data signal.
 10. The integrated circuit of claim 8, wherein the performance indicator is to be based at least on a measurement of a vertical eye opening of a received version of the data signal.
 11. An integrated circuit, comprising: a digital to analog converter (DAC) to produce, at a DAC output, a plurality of error sampler threshold voltages; a data sampler to compare a data signal to a data threshold voltage to produce a plurality of data samples; an error sampler to compare the data signal to the DAC output to produce a first error sample; and phase adjustment circuitry to, based on the first error sample and the plurality of data samples, adjust a phase difference between a timing reference and a clock signal that determines a timing that the data sampler and the error sampler sample the data signal.
 12. The integrated circuit of claim 11, wherein the first error sample is based on a comparison of the data signal to an early threshold voltage produced by the DAC.
 13. The integrated circuit of claim 12, wherein the first error sample is based on a comparison of the data signal to a late threshold voltage produced by the DAC.
 14. The integrated circuit of claim 13, further comprising: control circuitry to adjust the early threshold voltage and the late threshold voltage to optimize a figure-of-merit.
 15. The integrated circuit of claim 14, wherein adjusting the early threshold voltage and the late threshold voltage is to control a phase difference of the clock signal relative to transitions on the data signal.
 16. A method of operating an integrated circuit, comprising: comparing, at a first sampling time, a data signal to a first error threshold voltage to produce a first early error sample value; comparing, at the first sampling time, the data signal to at least a first data threshold voltage to produce a first data sample value; comparing, at a second sampling time, the data signal to a second error threshold voltage to produce a first late error sample value; comparing, at the second sampling time, the data signal to at least the first data threshold voltage to produce a second data sample value; based on the first early error sample value and the first data sample value, producing a first early error sample value; based on the first late error sample value and the second data sample value, producing a first late error sample value; and based on the first early error sample value and the first late error sample value, adjusting a phase relationship between the data signal and a timing reference signal that determines the first sampling time and the second sampling time.
 17. The method of claim 16, wherein the adjusting of the phase relationship between the data signal and the timing reference signal is to adjust a phase difference between the data signal and the timing reference signal to a first phase difference value.
 18. The method of claim 17, further comprising: while the phase difference between the data signal and the timing reference signal is operating at the first phase difference value, measuring a performance indicator.
 19. The method of claim 18, wherein the performance indicator is to be based on at least a bit error rate of a received version of the data signal.
 20. The method of claim 18, wherein the performance indicator is to be based at least on a measurement of a vertical eye opening of a received version of the data signal.
 21. The method of claim 18, further comprising: controlling a digital-to-analog converter to produce the first error threshold voltage and the second error threshold voltage. 